TY - GEN UR - http://lib.ugent.be/catalog/pug01:7240436 ID - pug01:7240436 LA - eng TI - Efficient hardware debugging using parameterized FPGA reconfiguration PY - 2016 PB - IEEE xplore 2016 AU - Kourfali, Alexandra UGent 000121006284 802001420579 975120506122 0000-0003-3430-1007 AU - Stroobandt, Dirk TW06 801000975717 0000-0002-4477-5313 AB - Functional errors and bugs inadvertently introduced at the RTL stage of the design process are responsible for the largest fraction of silicon IC re-spins. Thus, comprehensive func- tional verification is the key to reduce development costs and to deliver a product in time. The increasing demands for verification led to an increase in FPGA-based tools that perform emulation. These tools can run at much higher operating frequencies and achieve higher coverage than simulation. However, an important pitfall of the FPGA tools is that they suffer from limited internal signal observability, as only a small and preselected set of signals is guided towards (embedded) trace buffers and observed. This paper proposes a dynamically reconfigurable network of multiplexers that significantly enhance the visibility of internal signals. It allows the designer to dynamically change the small set of internal signals to be observed, virtually enlarging the set of observed signals significantly. These multiplexers occupy minimal space, as they are implemented by the FPGA’s routing infrastructure. ER -Download RIS file
| 00000nam^a2200301^i^4500 | |||
| 001 | 7240436 | ||
| 005 | 20190607145440.0 | ||
| 008 | 160601s2016------------------------eng-- | ||
| 024 | a 1854/LU-7240436 2 handle | ||
| 024 | a 10.1109/IPDPSW.2016.95 2 doi | ||
| 040 | a UGent | ||
| 245 | a Efficient hardware debugging using parameterized FPGA reconfiguration | ||
| 260 | b IEEE xplore c 2016 | ||
| 520 | a Functional errors and bugs inadvertently introduced at the RTL stage of the design process are responsible for the largest fraction of silicon IC re-spins. Thus, comprehensive func- tional verification is the key to reduce development costs and to deliver a product in time. The increasing demands for verification led to an increase in FPGA-based tools that perform emulation. These tools can run at much higher operating frequencies and achieve higher coverage than simulation. However, an important pitfall of the FPGA tools is that they suffer from limited internal signal observability, as only a small and preselected set of signals is guided towards (embedded) trace buffers and observed. This paper proposes a dynamically reconfigurable network of multiplexers that significantly enhance the visibility of internal signals. It allows the designer to dynamically change the small set of internal signals to be observed, virtually enlarging the set of observed signals significantly. These multiplexers occupy minimal space, as they are implemented by the FPGA’s routing infrastructure. | ||
| 598 | a C1 | ||
| 700 | a Kourfali, Alexandra u UGent 0 000121006284 0 802001420579 0 975120506122 0 0000-0003-3430-1007 9 2C1EACFE-6FE8-11E2-B41C-E1A910BDE39D | ||
| 700 | a Stroobandt, Dirk u TW06 0 801000975717 0 0000-0002-4477-5313 9 F4D6D3D0-F0ED-11E1-A9DE-61C894A0A6B4 | ||
| 650 | a Technology and Engineering | ||
| 653 | a TLUT | ||
| 653 | a TCON | ||
| 653 | a Reconfiguration | ||
| 653 | a FPGA | ||
| 653 | a Debugging | ||
| 653 | a Parameterised Configuration | ||
| 653 | a DCS | ||
| 773 | t 2016 IEEE International Parallel and Distributed Processing Symposium Workshops g 2016 IEEE International Parallel and Distributed Processing Symposium Workshops. 2016. IEEE xplore. p.277-282 q :<277 | ||
| 856 | 3 fullText u https://biblio.ugent.be/publication/7240436/file/7240453 z [open] y RAW.pdf | ||
| 920 | a confcontrib | ||
| Z30 | x EA 1 TW06 | ||
| 922 | a UGENT-EA | ||
All data below are available with an Open Data Commons Open Database License. You are free to copy, distribute and use the database; to produce works from the database; to modify, transform and build upon the database. As long as you attribute the data sets to the source, publish your adapted database with ODbL license, and keep the dataset open (don't use technical measures such as DRM to restrict access to the database).
The datasets are also available as weekly exports.
