TY - JOUR UR - http://lib.ugent.be/catalog/pug01:981220 ID - pug01:981220 LA - eng TI - Multirate cascaded discrete-time low-pass ΔΣ modulator for GSM/Bluetooth/UMTS PY - 2010 JO - (2010) IEEE JOURNAL OF SOLID-STATE CIRCUITS SN - 0018-9200 PB - 2010 AU - Bos, Lynn AU - Vandersteen, Gerd AU - Rombouts, Pieter TW06 801000963286 0000-0002-3731-9731 AU - Geis, Arnd AU - Morgado, Alonos AU - Rolain, Yves AU - Van der Plas, Geert AU - Ryckaert, Julien AB - This paper shows that multirate processing in a cascaded discrete-time Delta Sigma modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time Delta Sigma modulator by its adaptibility with the sampling frequency. The power reduction can be achieved by relaxing the sampling speed of the first stage and increasing it appropriately in the second stage. Furthermore, a cascaded Delta Sigma modulator enables the power efficient implementation of multiple communication standards. The advantages of multirate cascaded Delta Sigma modulators are demonstrated by comparing the performance of single-rate and multirate implementations using behavioral-level and circuit-level simulations. This analysis has been further validated with the design of a multirate cascaded triple-mode discrete-time Delta Sigma modulator. A 2-1 multirate low-pass cascade, with a sampling frequency of 80 MHz in the first stage and 320 MHz in the second stage, meets the requirements for UMTS. The first stage alone is suitable for digitizing Bluetooth and GSM with a sampling frequency of 90 and 50 MHz respectively. This multimode Delta Sigma modulator is implemented in a 1.2 V 90 nm CMOS technology with a core area of 0.076 mm(2). Measurement results show a dynamic range of 66/77/85 dB for UMTS/Bluetooth/GSM with a power consumption of 6.8/3.7/3.4 mW. This results in an energy per conversion step of 1.2/0.74/2.86 pJ. ER -Download RIS file
00000nam^a2200301^i^4500 | |||
001 | 981220 | ||
005 | 20161219154701.0 | ||
008 | 100618s2010------------------------eng-- | ||
022 | a 0018-9200 | ||
024 | a 000281763900010 2 wos | ||
024 | a 1854/LU-981220 2 handle | ||
024 | a 10.1109/JSSC.2010.2046240 2 doi | ||
040 | a UGent | ||
245 | a Multirate cascaded discrete-time low-pass ΔΣ modulator for GSM/Bluetooth/UMTS | ||
246 | a Multirate cascaded discrete-time low-pass delta sigma modulator for GSM/Bluetooth/UMTS | ||
260 | c 2010 | ||
520 | a This paper shows that multirate processing in a cascaded discrete-time Delta Sigma modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time Delta Sigma modulator by its adaptibility with the sampling frequency. The power reduction can be achieved by relaxing the sampling speed of the first stage and increasing it appropriately in the second stage. Furthermore, a cascaded Delta Sigma modulator enables the power efficient implementation of multiple communication standards. The advantages of multirate cascaded Delta Sigma modulators are demonstrated by comparing the performance of single-rate and multirate implementations using behavioral-level and circuit-level simulations. This analysis has been further validated with the design of a multirate cascaded triple-mode discrete-time Delta Sigma modulator. A 2-1 multirate low-pass cascade, with a sampling frequency of 80 MHz in the first stage and 320 MHz in the second stage, meets the requirements for UMTS. The first stage alone is suitable for digitizing Bluetooth and GSM with a sampling frequency of 90 and 50 MHz respectively. This multimode Delta Sigma modulator is implemented in a 1.2 V 90 nm CMOS technology with a core area of 0.076 mm(2). Measurement results show a dynamic range of 66/77/85 dB for UMTS/Bluetooth/GSM with a power consumption of 6.8/3.7/3.4 mW. This results in an energy per conversion step of 1.2/0.74/2.86 pJ. | ||
598 | a A1 | ||
700 | a Bos, Lynn | ||
700 | a Vandersteen, Gerd | ||
700 | a Rombouts, Pieter u TW06 0 801000963286 0 0000-0002-3731-9731 9 F4D05B04-F0ED-11E1-A9DE-61C894A0A6B4 | ||
700 | a Geis, Arnd | ||
700 | a Morgado, Alonos | ||
700 | a Rolain, Yves | ||
700 | a Van der Plas, Geert | ||
700 | a Ryckaert, Julien | ||
650 | a Technology and Engineering | ||
653 | a Cascade | ||
653 | a CMOS | ||
653 | a CONVERSION | ||
653 | a DYNAMIC-RANGE | ||
653 | a delta sigma modulation | ||
653 | a multimode | ||
653 | a multirate | ||
653 | a sigma delta modulation | ||
773 | t IEEE JOURNAL OF SOLID-STATE CIRCUITS g IEEE J. Solid-State Circuit. 2010. 45 (6) p.1198-1208 q 45:6<1198 | ||
856 | 3 Full Text u https://biblio.ugent.be/publication/981220/file/981263 z [ugent] y LynnBOss_JSSC_2010.pdf | ||
920 | a article | ||
Z30 | x EA 1 TW06 | ||
922 | a UGENT-EA |
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