TY - GEN UR - http://lib.ugent.be/catalog/pug01:1339511 ID - pug01:1339511 LA - eng TI - Today's high level synthesis tools: a comparison PY - 2010 PB - 2010 AU - Meeus, Wim AU - Stroobandt, Dirk TW06 801000975717 0000-0002-4477-5313 AB - High-level synthesis (HLS) tools greatly reduce the effort required in Register Transfer Level (RTL) design by automatically converting behavioral algorithms into synthesizable hardware descriptions. These tools are being actively developed, and even though they have been around for more than 10 years, they have only recently been adopted by industry. As a result of the reduced designer effort, advantages of high level synthesis include an improved time to market and the possibility to do extensive design space exploration. In this work, we present a comparison of some of today's tools based on our own experience of implementing an image processing algorithm. Different features are highlighted, such as design entry, capabilities, synthesis results, verification options and the learning curve for the designer. We have found that the high-level synthesis tools greatly differ in their features and also in the types of applications they can handle. Because of design space exploration capabilities, the quality of HLS generated hardware is comparable to manual RTL design, in terms of area, latency and also power consumption. Among the tools that we have evaluated so far, the most impressive results were obtained using Catapult C from Mentor Graphics. ER -Download RIS file
| 00000nam^a2200301^i^4500 | |||
| 001 | 1339511 | ||
| 005 | 20180813140845.0 | ||
| 008 | 110624s2010------------------------eng-- | ||
| 024 | a 1854/LU-1339511 2 handle | ||
| 040 | a UGent | ||
| 245 | a Today's high level synthesis tools: a comparison | ||
| 260 | c 2010 | ||
| 520 | a High-level synthesis (HLS) tools greatly reduce the effort required in Register Transfer Level (RTL) design by automatically converting behavioral algorithms into synthesizable hardware descriptions. These tools are being actively developed, and even though they have been around for more than 10 years, they have only recently been adopted by industry. As a result of the reduced designer effort, advantages of high level synthesis include an improved time to market and the possibility to do extensive design space exploration. In this work, we present a comparison of some of today's tools based on our own experience of implementing an image processing algorithm. Different features are highlighted, such as design entry, capabilities, synthesis results, verification options and the learning curve for the designer. We have found that the high-level synthesis tools greatly differ in their features and also in the types of applications they can handle. Because of design space exploration capabilities, the quality of HLS generated hardware is comparable to manual RTL design, in terms of area, latency and also power consumption. Among the tools that we have evaluated so far, the most impressive results were obtained using Catapult C from Mentor Graphics. | ||
| 598 | a C3 | ||
| 100 | a Meeus, Wim u TW06 0 801001082518 | ||
| 700 | a Stroobandt, Dirk u TW06 0 801000975717 0 0000-0002-4477-5313 | ||
| 650 | a Technology and Engineering | ||
| 653 | a Behavioral synthesis | ||
| 653 | a Electronic design automation | ||
| 653 | a High level synthesis | ||
| 653 | a Electronic system level | ||
| 773 | t STW.ICT Conference (PRORISC - 2010) g STW.ICT conference, Abstracts. 2010. q :< | ||
| 856 | 3 Full Text u https://biblio.ugent.be/publication/1339511/file/1339558 z [open] y abstract.pdf | ||
| 920 | a confcontrib | ||
| 852 | x EA b TW06 | ||
| 922 | a UGENT-EA | ||
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